High voltage silicon carbide (SiC) devices can be capable of handling high voltages, and may handle as much as about 100 amps or more of current, depending on the size of their active area. High voltage SiC devices have a number of important applications, particularly in the field of power conditioning, distribution and control.
A conventional power device structure has an n-type SiC substrate on which an n− epitaxial layer, which functions as a drift region, is formed. The device typically includes a P-N and/or Schottky junction on the n-layer, which acts as a main junction for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. A p-type junction termination extension (JTE) region, which is typically formed by ion implantation, may surround the main junction. The implants used to form the JTE region may be aluminum, boron, or any other suitable p-type dopant. The purpose of the JTE region is to reduce or prevent the electric field crowding at the edges, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. Other termination techniques include guard rings and floating field rings that may be more strongly influenced by surface effects. A channel stop region may also be formed by implantation of n-type dopants, such as nitrogen or phosphorus, in order to prevent/reduce extension of the depletion region to the edge of the device.
In addition to junction termination extension (JTE), multiple floating guard rings (MFGR) and field plates (FP) are commonly used termination schemes in high voltage silicon carbide devices. Another conventional edge termination technique is a mesa edge termination.
Field plate termination is also a conventional technique for edge termination of a device and may be cost-effective. In conventional field plate devices, high fields are supported by the oxide layer under the metal field plate. This technique performs well for silicon devices where the highest field in the semiconductor is relatively low. However, in SiC devices the electric fields in the blocking state may be very high (˜2 MV/cm) which multiplies by a factor of 2.5 at the oxide-semiconductor interface. This leads to very high oxide fields and may result in long-term reliability problems. Thus, field plate terminations may be unsuitable for use in SiC devices.
The use of multiple floating guard rings in addition to JTE has been proposed as a technique for reducing the sensitivity of the JTE to implant dose variation. See Kinoshita et al., “Guard Ring Assisted RESURF: A New Termination Structure Providing Stable and High Breakdown Voltage for SiC Power Devices,” Tech. Digest of ISPSD '02, pp. 253-256. Kinoshita et al. reported that such techniques reduced the sensitivity to implant dose variation. However, the area utilized for termination was increased to almost three times the area of JTE alone as the guard rings are added to both the inner edge of the JTE and the outside of the JTE.
A conventional JTE-terminated Schottky diode is illustrated in FIG. 1. As shown therein, a Schottky diode 10 includes an n− drift layer 12 on an n+ substrate 14. FIG. 1 illustrates one half of a Schottky diode structure; the structure may include mirror image portions (not shown). An anode Schottky contact 23 is on the drift layer 12, and a cathode contact 25 is on the n+ substrate 14. A junction termination extension (JTE) region 20 including a plurality of JTE zones 20A, 20B, 20C is provided in the n− drift layer 12 adjacent to the Schottky contact 23. The JTE zones 20A, 20B, 20C are p-type regions that may have levels of charge that decrease outwardly in a stepwise fashion with distance from the Schottky junction. Although three JTE zones 20A, 20B, 20C are illustrated, more or fewer JTE zones may be provided.
The JTE zones 20A, 20B, 20C may be formed by successive implantation of ions into the n− drift layer 12. However, such implantation may require multiple mask and implantation steps, increasing the complexity and expense of production. This may be exacerbated as the number of JTE zones is increased. Furthermore, the stepwise doping gradient provided by such an approach may not provide an ideal termination.
Additional conventional terminations of SiC Schottky diodes are described in “Planar Terminations in 4H—SiC Schottky Diodes With Low Leakage And High Yields” by Singh et al., ISPSD '97, pp. 157 160. A p-type epitaxy guard ring termination for a SiC Schottky Barrier Diode is described in “The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes” by Ueno et al., IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331 332. Additionally, other termination techniques are described in published PCT Application No. WO 97/08754 entitled “SiC Semiconductor Device Comprising A PN Junction With A Voltage Absorbing Edge.”
Another type of junction termination is disclosed in U.S. Pat. No. 7,026,650, which is assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference as if set forth fully.
A junction barrier Schottky (JBS) diode with a guard ring termination is illustrated in FIGS. 2 and 3. FIG. 2 is a cross sectional illustration of a junction barrier Schottky diode 30 with a guard ring edge termination, while FIG. 3 is a plan view of the junction barrier Schottky diode 30 without the Schottky contact. It will be appreciated that the structure of a JBS diode is similar to that of a merged P-N junction Schottky (MPS) diode, although the operation of the devices is slightly different in forward conduction mode. References to JBS diode structures herein are intended to refer to similar MPS structures as well.
The device 30 includes a silicon carbide substrate 14. The substrate may be doped with dopants having a first conductivity type, and may have a polytype of 2H, 4H, 6H, 3C and/or 15R.
The device 30 includes a lightly doped drift layer 12 of the first conductivity type. A Schottky contact 34 forms a Schottky barrier junction with the drift layer 12. A cathode contact 46 is on the n-type substrate 14.
A guard ring structure is provided at and extending beneath the surface of the drift layer 12 adjacent the Schottky junction between the Schottky contact 34 and the drift layer 12. The guard ring structure includes a plurality of guard rings 38 of a second conductivity type that form concentric rings around the active region of the device (i.e., the region including the Schottky junction). The guard rings 38 may be formed, for example, by ion implantation. Guard ring formation is described in detail in U.S. Pat. No. 7,026,650 entitled “Multiple Floating Guard Ring Edge Termination for Silicon Carbide Devices” issued on Apr. 11, 2006 and U.S. Publication No. 2006/0118792 entitled “Edge Termination Structures For Silicon Carbide Devices And Methods Of Fabricating Silicon Carbide Devices Incorporating Same” published on Jun. 8, 2006, which are assigned to the assignee of the present invention and which are incorporated herein by reference.
Also included in the structure is a lightly doped region 36 of the second conductivity type that is provided between the guard rings 38 at the surface of the drift layer 12. The lightly doped region 36 may extend outside the outermost guard ring 38, and may be formed to a depth in the drift layer 12 that is less than the depth to which the guard rings extend. In some embodiments, the lightly doped region 36 may provide a surface charge compensation region as discussed, for example in the above referenced U.S. Pat. No. 7,026,650 and U.S. Publication No. 2006/0118792. In some other embodiments, the lightly doped region may provide a reduced surface field (RESURF) region at the surface of the drift layer, as discussed, for example, in U.S. Pat. No. 7,026,650 and U.S. Publication No. 2006/0118792. The lightly doped region 36 may extend completely or incompletely between adjacent guard rings 38. Furthermore, the lightly doped region 36 may extend deeper or shallower into the drift layer 12 than the guard rings 38.
The device 30 further includes a plurality of junction barrier regions 42 of the second conductivity type at the surface of the drift layer 12 opposite the substrate 14. The junction barrier regions 42 may also be formed by ion implantation. In some embodiments, the junction barrier regions 42 may have a structure as shown in U.S. Publication No. 2006/0255423, which is assigned to the assignee of the present invention, and the disclosure of which is incorporated herein by reference.
The Schottky diode may also have a structure as shown in U.S. Publication No., 2009/0289262, U.S. Publication No 2008/0029838, U.S. Pat. No. 7,728,402 and/or U.S. Publication No. 2009/0289262, which are assigned to the assignee of the present invention, and the disclosures of which are incorporated herein by reference.
The Schottky contact 34 contacts the junction barrier regions 42. When a reverse bias is applied to the device, a depletion region generated at the p-n junction between the junction barrier regions 42 and the drift layer 12 sustains the reverse bias and thereby protects the Schottky junction.
Semiconductor power devices are designed to block (in the reverse blocking state) or pass (in the forward operating state) large levels of voltage and/or current. For example, in the reverse blocking state, a semiconductor power device may be designed to sustain hundreds to thousands of volts of electric potential. However, at high reverse voltages, a semiconductor power device may begin to let some current flow through the device. Such current, described as “leakage current” may be highly undesirable. Leakage current may begin to flow if the reverse voltage is increased beyond the design voltage blocking capability of the device, which is typically a function of the doping and thickness of the drift layer. However, leakage can occur for other reasons, such as failure of the edge termination and/or the primary junction of the device.